A low-power, high-speed DCT architecture for image compression: Principle and implementation.
Maher JridiAyman AlfalouPublished in: VLSI-SoC (2010)
Keyphrases
- low power
- high speed
- image compression
- vlsi architecture
- cmos technology
- discrete cosine transform
- power consumption
- low cost
- signal processor
- low bit rate
- low power consumption
- wavelet transform
- subband
- single chip
- ultra low power
- real time
- compression ratio
- compressed images
- vlsi circuits
- compression algorithm
- design considerations
- nm technology
- reconstructed image
- vlsi implementation
- mixed signal
- cmos image sensor
- image sensor
- digital signal processing
- entropy coding
- design methodology
- image processing
- image transmission
- analog to digital converter
- gate array