Reconfigurable Deep Learning Accelerator Hardware Architecture Design for Sparse CNN.

Chung-Bin Wu Chung-Hsuan Chen Chen-Peng Kuan

Published in: ICCE-TW (2021)

Keyphrases

hardware architecture
deep learning
field programmable gate array
hardware implementation
hardware architectures
semi supervised
general purpose
unsupervised feature learning
feature space
supervised learning
associative memory