Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction.
Aman GoelKarem A. SakallahPublished in: NFM (2019)
Keyphrases
- model checking
- hardware description language
- integrated circuit
- hardware designs
- model based diagnosis
- bounded model checking
- temporal logic
- formal verification
- high level
- temporal properties
- model checker
- finite state
- finite state machines
- computation tree logic
- formal specification
- partial order reduction
- process algebra
- timed automata
- verification method
- pspace complete
- formal methods
- epistemic logic
- symbolic model checking
- automated verification
- natural language
- linear temporal logic
- reachability analysis
- concurrent systems
- transition systems
- deterministic finite automaton
- reactive systems
- operational semantics
- planning domains
- alternating time temporal logic
- knowledge based systems