Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme.
Mohamed B. AbdelhalimSerag E.-D. HabibPublished in: ISVLSI (2008)
Keyphrases
- hw sw
- upper bound
- hardware software
- hardware software partitioning
- embedded systems
- field programmable gate array
- lower bound
- hardware and software
- hardware implementation
- hardware design
- hardware architecture
- hardware software co design
- low cost
- design methodology
- real time
- power consumption
- neural network
- computing systems
- image processing
- feature analysis
- computational power
- multithreading
- software systems
- signal processing