Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography.
K. Sathish ShetA. R. AswathM. C. HanumantharajuXiao-Zhi GaoPublished in: Multim. Tools Appl. (2019)
Keyphrases
- high speed
- field programmable gate array
- hardware implementation
- reconfigurable architecture
- low power
- low cost
- distance measure
- digital signal
- systolic array
- empirical mode decomposition
- real time
- data acquisition
- digital signal processors
- heterogeneous computing
- functional units
- frame rate
- power reduction
- embedded systems
- interconnection networks
- high speed networks
- parallel architectures
- fpga implementation
- fine grain
- hardware design
- general purpose
- neural network
- reconfigurable hardware
- compute intensive
- smart camera