High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator.
Chung-Bin WuYin-Tsung HwangYu-Cheng HsuehYu-Kuan HsiaoPublished in: ISOCC (2020)
Keyphrases
- deep learning
- hardware design
- bandwidth utilization
- hardware implementation
- artificial intelligence
- machine learning
- field programmable gate array
- computer vision
- real time
- unsupervised feature learning
- fpga hardware
- higher order
- efficient implementation
- unsupervised learning
- signal processing
- image processing
- learning algorithm