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High-Level Synthesis Considering Layer Assignment on Timing in 3D-IC.

Myeongwoo JinDoekkeun OhJuho Kim
Published in: ISOCC (2022)
Keyphrases
  • high level synthesis
  • integrated circuit
  • parallel architecture
  • design space exploration
  • multi layer
  • neural network
  • case study
  • real world
  • scheduling problem
  • parallel processing