An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology.
Tim HansmeierMarco PlatznerMd Jubaer Hossain PanthoDavid AndrewsPublished in: J. Signal Process. Syst. (2019)
Keyphrases
- field programmable gate array
- case study
- memory usage
- rapid development
- key technologies
- real time
- low cost
- high speed
- automatic theorem proving
- compute intensive
- computer systems
- cost effective
- gate array
- theorem proving
- data processing
- signal processing
- high resolution
- hardware implementation
- image processing algorithms
- parallel computing
- data acquisition
- memory size
- real time image processing
- parallel hardware
- multi dimensional