COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks Based on Systolic Array.
Chen XinQiang ChenMiren TianMohan JiChenglong ZouXin'an WangBo WangPublished in: ICPADS (2017)
Keyphrases
- hardware architecture
- systolic array
- convolutional neural networks
- hardware implementation
- parallel architecture
- reconfigurable architecture
- data flow
- energy efficient
- convolutional network
- wireless sensor networks
- hardware architectures
- sensor networks
- associative memory
- field programmable gate array
- processing elements
- efficient implementation
- neural network
- parallel processing
- energy efficiency
- signal processing
- artificial neural networks
- support vector
- kernel methods
- object oriented
- multiscale
- bayesian networks
- block matching motion estimation
- feature extraction
- computer vision