Reconfigurable Parallel Architecture of High Speed Round Robin Arbiter.
Arnab PaulMamdudul Haque KhanM. Muktadir RahmanTanvir Zaman KhanPrajoy PodderMd. Yeasir Akram KhanPublished in: CoRR (2020)
Keyphrases
- round robin
- parallel architecture
- high speed
- systolic array
- hardware implementation
- load balancing
- parallel processing
- shared memory
- low power
- high level synthesis
- load balance
- signal processing
- distributed memory
- parallel implementation
- real time
- low cost
- efficient implementation
- data flow
- field programmable gate array
- processing elements
- markov random field
- rough sets
- probabilistic model
- decision trees
- computer vision
- data mining