Reusable context pipelining for low power coarse-grained reconfigurable architecture.
Yoonjin KimRabi N. MahapatraPublished in: IPDPS (2008)
Keyphrases
- low power
- coarse grained
- fine grained
- reconfigurable architecture
- low cost
- power consumption
- high speed
- single chip
- wireless transmission
- digital signal processing
- high power
- cmos technology
- logic circuits
- vlsi architecture
- mixed signal
- delay insensitive
- protein sequences
- systolic array
- vlsi circuits
- high level
- multithreading
- low power consumption
- information retrieval
- power reduction
- low voltage
- real time
- natural language processing
- image sensor
- parallel processing