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Bolt: A Stateful Processor Interconnect.
Felix Sutton
Marco Zimmerling
Reto Da Forno
Roman Lim
Tonio Gsell
Georgia Giannopoulou
Federico Ferrari
Jan Beutel
Lothar Thiele
Published in:
SenSys (2015)
Keyphrases
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high speed
low power
parallel processing
clock frequency
multiprocessor systems
input output
databases
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single chip
computer architecture
ibm eservertm
instruction set
parallel architecture
high end
case study
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genetic algorithm
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