Modular model checking of VLSI designs described in VHDL.
Fahim Rahim-SarwaryEmmanuelle EncrenazMichel MinouxRajesh K. BawaPublished in: CATA (1998)
Keyphrases
- model checking
- temporal logic
- formal specification
- formal verification
- model checker
- symbolic model checking
- automated verification
- computation tree logic
- temporal properties
- partial order reduction
- process algebra
- finite state
- verification method
- timed automata
- epistemic logic
- linear temporal logic
- bounded model checking
- asynchronous circuits
- reachability analysis
- finite state machines
- planning domains
- reactive systems
- deterministic finite automaton
- pspace complete
- np complete
- formal methods
- satisfiability problem
- modal logic
- heuristic search