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Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation.
Jean Pierre T. Habimana
Francis Sabado
Jia Di
Published in:
ISCAS (2016)
Keyphrases
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design methodology
delay insensitive
asynchronous circuits
high speed
countermeasures
case study
neural network
expert systems
evolutionary algorithm
fuzzy neural network
chip design
object oriented
physical design