A Low Bit Architecture for a Very Compact Hardware Implementation of the AES Algorithm.
Abdullah Haroon RasheedMuhammad EssamUmair KhalidShoab Ahmed KhanSheikh Muhammad FarhanPublished in: ISSA (2006)
Keyphrases
- hardware implementation
- software implementation
- fpga implementation
- pipeline architecture
- image processing algorithms
- hardware architecture
- signal processing
- efficient implementation
- parallel architecture
- fpga device
- learning algorithm
- dedicated hardware
- k means
- hardware design
- pipelined architecture
- image processing
- fractal encoding
- real time
- euler number
- fpga technology
- optimal solution
- machine learning