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A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract).
David Jefferson
Srinivas Reddy
Christopher Lane
Ninh Ngo
Wanli Chang
Manuel Mijia
Ketan Zaveri
Cameron McClintock
Richard Cliff
Published in:
FPGA (1998)
Keyphrases
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programmable logic
high speed
power consumption
field programmable gate array
cmos technology
field effect transistors
computer vision
case study
high level
cooperative
pattern recognition
multi agent systems
pairwise
steady state
multiple input
nm technology