Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files.

Rahul Singh Gi-Moon Hong Suhwan Kim

Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2013)

Keyphrases

low power
power consumption
low cost
high speed
high power
single chip
digital signal processing
vlsi architecture
wireless transmission
image sensor
logic circuits
vlsi circuits
file system
hardware and software
power saving
shortest path
network structure
delay insensitive