Design of a 5.2-GHz CMOS Power Amplifier Using TF-Based 2-Stage Dual-Radial Power Splitting/Combining Architecture.
Jeng-Han TsaiPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2019)
Keyphrases
- power consumption
- high power
- power dissipation
- nm technology
- chip design
- power management
- low power
- design process
- cmos technology
- architectural design
- high speed
- real time
- design considerations
- design methodology
- single chip
- design principles
- software architecture
- case study
- cmos image sensor
- ultra low power
- power supply
- distributed architecture
- low cost
- management system