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A highly linear CMOS APS circuit for column-parallel readout with improved gain and process tolerance.

P. AnandG. N. ArvindBalan Bhuvan
Published in: ICECS (2020)
Keyphrases
  • high speed
  • analog vlsi
  • real time
  • circuit design
  • low voltage
  • neural network
  • genetic algorithm
  • low cost
  • vlsi circuits