A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing.
Mingqiang GuoLiang QiWeibing ZhaoGang XiaoRui Paulo MartinsSai-Weng SinPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2023)