A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration.
Evelina FornoAndrea AcquavivaYuki KobayashiEnrico MaciiGianvito UrgesePublished in: VLSI-SoC (2018)
Keyphrases
- hardware architecture
- annealing algorithm
- processing elements
- hardware implementation
- protein folding
- hardware architectures
- deterministic annealing
- parallel processing
- simulated annealing algorithm
- parallel implementation
- fine grained
- simulated annealing
- field programmable gate array
- computer vision
- shared memory
- global optimization
- graphical models
- artificial neural networks