Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology.
Guan-Sing ChenChin-Yang WuChen-Lun LinHao-Wei HungJri LeePublished in: A-SSCC (2014)
Keyphrases
- cmos technology
- fully integrated
- pattern generator
- bit error rate
- ultra wideband
- modulation scheme
- low power
- high speed
- computer simulation
- multipath
- signal to noise ratio
- power consumption
- channel coding
- parallel processing
- analytical model
- low voltage
- wireless channels
- power dissipation
- low cost
- workflow management
- image sensor
- communication systems
- ofdm system
- silicon on insulator
- routing algorithm
- end to end