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Low-Voltage Class-AB CMOS Output Stage with Tunable Quiescent Current.

Zhenpeng BianRuohe YaoFei Luo
Published in: IEICE Trans. Electron. (2010)
Keyphrases
  • low voltage
  • design considerations
  • power line
  • cmos technology
  • random access memory
  • power management
  • pattern recognition