Low-Power 32bit×32bit Multiplier Design with Pipelined Block-Wise Shutdown.
Yong-Ju JangYoan ShinMin-Cheol HongJae-Kyung WeeSeongsoo LeePublished in: HiPC (2005)
Keyphrases
- low power
- single chip
- block wise
- power consumption
- analog to digital converter
- low power consumption
- low cost
- high speed
- vlsi architecture
- gate array
- nm technology
- logic circuits
- digital signal processing
- power dissipation
- mixed signal
- cmos technology
- instruction set architecture
- ground truth
- power reduction
- vlsi circuits
- multiresolution
- image sensor
- signal processing