Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes.
Yunlong ZhangQiang TongLi LiWei WangKen ChoiJongEun JangHyobin JungSi-Young AhnPublished in: ISOCC (2012)
Keyphrases
- low power
- power consumption
- power reduction
- power dissipation
- single chip
- low cost
- low power consumption
- logic circuits
- high speed
- vlsi architecture
- clock gating
- gate array
- digital signal processing
- mixed signal
- cmos technology
- design methodology
- design process
- vlsi circuits
- ultra low power
- power saving
- design considerations
- multi channel
- fine grained