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Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors.
Hongyin Luo
Shaojun Wei
Deming Chen
Donghui Guo
Published in:
J. Parallel Distributed Comput. (2014)
Keyphrases
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high speed
analog vlsi
circuit design
multithreading
chip design
cmos technology
low power
power dissipation
neural network
switched networks
phase locked loop
parallel algorithm
power consumption
parallel computing
micron cmos