Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic.
Ayse Neslin IsmailogluMurat AskarPublished in: ICECS (2008)
Keyphrases
- model checking
- linear array
- verification method
- high speed
- asynchronous circuits
- face verification
- data structure
- higher level
- model checker
- automated reasoning
- levels of abstraction
- shift register
- random access memory
- formal verification
- neural network
- data flow
- modal logic
- linear programming
- multi agent systems
- genetic algorithm