Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications.
Jitendra Kumar MishraPrasanna Kumar MisraManish GoswamiPublished in: APCCAS (2020)
Keyphrases
- low power
- power consumption
- single chip
- low cost
- low power consumption
- cmos technology
- high speed
- vlsi architecture
- logic circuits
- digital signal processing
- power dissipation
- high power
- power reduction
- mixed signal
- wireless transmission
- energy dissipation
- gate array
- low voltage
- ultra low power
- power management
- nm technology
- real time
- design process