Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.
Marius MeyerTobias KenterChristian PlesslPublished in: H2RC@SC (2020)
Keyphrases
- benchmark suite
- field programmable gate array
- hardware implementation
- parallel computing
- embedded systems
- hardware architecture
- real time
- signal processing
- image processing algorithms
- randomly selected
- high speed
- computing systems
- parallel implementation
- fpga implementation
- transactional memory
- low power consumption
- parallel programming
- low cost
- programming language