A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS.
Sami Ur RehmanMohammad Mahdi KhafajiAli FerschischiCorrado CartaFrank EllingerPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2020)