An integrated approach to reducing power dissipation in memory hierarchies.
Jayaprakash PisharathAlok N. ChoudharyPublished in: CASES (2002)
Keyphrases
- power dissipation
- power reduction
- power consumption
- low power
- cmos technology
- chip design
- logic circuits
- finite state machines
- low cost
- nm technology
- memory requirements
- design methodology
- flip flops
- digital signal processing
- network on chip
- multithreading
- high speed
- short circuit
- massively parallel
- real time
- signal processing
- image analysis
- neural network