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Low-power design of variable block-size LDPC decoder using nanometer technology.
Chih-Hung Lin
Alex Chien-Lin Huang
Robert Chen-Hao Chang
Kuang-Hao Lin
Published in:
ISCAS (2010)
Keyphrases
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low power
gate array
cmos technology
low density parity check
vlsi architecture
power consumption
low cost
logic circuits
low power consumption
high speed
nm technology
low complexity
ldpc codes
decoding algorithm
power dissipation
variable block size
motion estimation
quadtree
ultra low power