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Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications.

Haonan WangKe ChenChenggang YanBi WuWeiqiang Liu
Published in: MWSCAS (2023)
Keyphrases
  • error tolerant
  • graph matching
  • low cost
  • hardware implementation
  • field programmable gate array
  • pattern recognition
  • subgraph isomorphism
  • hardware design
  • hardware architecture