Low power sensor node processor architecture.
Goran PanicThomas BasmerKlaus Tittelbach-HelmrichLukasz LopacinskiPublished in: ICECS (2010)
Keyphrases
- low power
- energy dissipation
- high speed
- single chip
- power consumption
- vlsi architecture
- energy efficiency
- low cost
- wireless sensor networks
- gate array
- sensor nodes
- sensor networks
- cmos technology
- mixed signal
- energy consumption
- data transmission
- real time
- nm technology
- energy efficient
- data acquisition
- low power consumption
- routing protocol
- mobile sensor networks
- logic circuits
- power reduction
- image sensor
- sensor data
- node selection
- resource constrained
- response time
- low complexity