BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels.
Amir-Mohammad RahmaniPasi LiljebergJuha PlosilaHannu TenhunenPublished in: ISVLSI (2010)
Keyphrases
- multi processor
- network on chip
- routing algorithm
- packet switched
- shared memory
- single processor
- network simulator
- program execution
- data transfer
- multi core processors
- power dissipation
- distributed memory
- computationally efficient
- real time
- fault tolerant
- interconnection networks
- computer networks
- heuristic search
- knowledge base