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Low-power and high-speed shift-based multiplier for error tolerant applications.
Sami Malek
Sarah Abdallah
Ali Chehab
Imad H. Elhajj
Ayman I. Kayssi
Published in:
Microprocess. Microsystems (2017)
Keyphrases
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low power
error tolerant
high speed
graph matching
low cost
single chip
low power consumption
vlsi architecture
hardware implementation
subgraph isomorphism
power consumption
real time
vlsi circuits
association patterns
gate array
logic circuits
cmos technology
image sensor
ultra low power