Runtime leakage power estimation technique for combinational circuits.

Yu-Shiang Lin Dennis Sylvester

Published in: ASP-DAC (2007)

Keyphrases

asynchronous circuits
logic circuits
power consumption
high speed
estimation algorithm
power dissipation
density estimation
accurate estimation
chip design
power reduction
database
maximum likelihood estimation
analog circuits
circuit design
maximum likelihood
website
neural network
real time