Verifying Chips Design at RTL Level.

Wu Wang Nan Zhang Cong Tian Zhenhua Duan Zhijie Xu Chaofeng Yu

Published in: TASE (2023)

Keyphrases

high speed
building blocks
design process
design space
neural network
artificial intelligence
case study
user interface
software development
software architecture
engineering design
integrated circuit
levels of abstraction
optimal design
knowledge level
chip design