A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC.
Chenhao GuLeilei HuangXiaoyang ZengYibo FanPublished in: VLSI-SoC (2019)
Keyphrases
- hardware architecture
- motion estimation
- video compression
- low complexity
- hardware implementation
- video coding
- coding efficiency
- motion compensated
- block matching motion estimation
- motion compensation
- video codec
- reference frame
- hardware architectures
- motion vectors
- video coding standard
- inter frame
- source code
- rate distortion
- field programmable gate array
- video compression standard
- image sequences
- computational complexity
- processing elements
- spatial domain
- optical flow
- video sequences
- associative memory
- block matching
- floating point
- intra prediction
- early termination
- software systems
- general purpose
- artificial neural networks
- machine learning