Reveal: A Formal Verification Tool for Verilog Designs.

Zaher S. Andraus Mark H. Liffiton Karem A. Sakallah

Published in: LPAR (2008)

Keyphrases

formal verification
model checking
model checker
bounded model checking
symbolic model checking
automated verification
program slicing
software engineering
temporal logic
artificial intelligence
orders of magnitude
design tools
formal methods
design space