Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.
Ethiopia NigussieSampo TuunaJuha PlosilaPasi LiljebergJouni IsoahoHannu TenhunenPublished in: IET Circuits Devices Syst. (2011)
Keyphrases
- delay insensitive
- low power
- bit parallel
- power dissipation
- cmos technology
- power consumption
- high speed
- pattern matching
- low cost
- single chip
- chip design
- regular expressions
- digital signal processing
- image sensor
- learning algorithm
- high bandwidth
- ensemble learning
- ensemble methods
- combining multiple
- asynchronous circuits
- machine learning
- cost sensitive
- query processing
- feature selection
- weak classifiers
- lower cost
- physical design
- input output
- query language
- fiber optic
- deblocking filter