High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs.
Muzaffar RaoThomas NeweIan Andrew GroutAvijit MathurPublished in: J. Circuits Syst. Comput. (2016)
Keyphrases
- hardware implementation
- reconfigurable hardware
- high speed
- field programmable gate array
- low cost
- fpga device
- hardware software
- efficient implementation
- fpga technology
- hardware architecture
- fpga implementation
- low power
- hardware design
- signal processing
- embedded systems
- image processing algorithms
- image processing
- parallel architecture
- parallel computing
- machine learning
- implementation details
- functional units
- massively parallel
- evolvable hardware
- fine grain
- processing elements
- real time
- hardware and software
- data sets