A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices.
SwatiRanajoy SadhukhanMitul Sudhirkumar NagarPinalkumar EngineerPublished in: iSES (2023)
Keyphrases
- memory efficient
- neural network
- external memory
- pattern recognition
- artificial neural networks
- high speed
- probabilistic inference
- iterative deepening
- back propagation
- reconfigurable hardware
- low power consumption
- single chip
- inference process
- neural network model
- mobile devices
- embedded systems
- field programmable gate array
- low cost
- feed forward
- real time image processing
- multiple sequence alignment
- neural nets
- multi layer
- genetic algorithm
- image processing
- fast fourier transform
- real time
- hardware architecture
- bayesian networks
- hardware design
- probabilistic model
- recurrent neural networks