Using partial reconfiguration and high-level models to accelerate FPGA design validation.
Yousef IskanderStephen D. CravenAthira ChandrasekharanSureshwar RajagopalanGuruprasad SubbarayanTannous FrangiehCameron D. PattersonPublished in: FPT (2010)
Keyphrases
- high level
- design space
- image processing
- probabilistic model
- model validation
- modelling language
- statistical models
- verilog hdl
- process model
- design process
- higher level
- source code
- low level
- hardware design
- single chip
- complex systems
- hardware implementation
- metamodel
- efficient implementation
- real time
- prior knowledge
- case study
- learning algorithm
- neural network