An MDE-based approach to the verification of SysML state machine diagram.

Xiaopu Huang Qingqing Sun Jiangwei Li Minxue Pan Tian Zhang

Published in: Internetware (2012)

Keyphrases

state machine
formal methods
state machines
fault tolerant
finite state machines
model checking
safety analysis
modeling language
state transition
formal verification
model checker
safety critical
control system
real time
temporal logic
digital libraries
symbolic model checking
databases