A Low Power 16-bit 125MS/s Pipeline ADC with 100dB SFDR.
Xiaodan ZhouWeipeng HeChen SuTao LiuDongbing FuQiang LiPublished in: ISCAS (2024)
Keyphrases
- low power
- analog to digital converter
- single chip
- mixed signal
- low cost
- power consumption
- high speed
- image sensor
- high power
- vlsi circuits
- wireless transmission
- low power consumption
- logic circuits
- digital signal processing
- gate array
- vlsi architecture
- cmos technology
- delay insensitive
- digital camera
- cmos image sensor
- signal processing
- real time
- power dissipation
- power reduction
- design methodology
- multi channel