A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath.
Yeong-Kang LaiHan-Jen HsuPublished in: ISCAS (2) (2003)
Keyphrases
- cost effective
- low cost
- systolic array
- digital signal
- single chip
- reconfigurable architecture
- cost effectiveness
- functional units
- parallel architecture
- computation intensive
- hardware implementation
- high speed
- reduces the computational complexity
- data center
- general purpose
- low power
- computer architecture
- parallel processing
- information and communication technologies
- real time
- multi core processors
- fine grain
- operating system
- processing elements
- parallel processors
- general purpose processors
- distributed memory