Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits.
Christian PachaKlaus von ArnimFlorian BauerThomas SchulzWade XiongK. T. SanAndrew MarshallThomas BaumannC. Rinn CleavelinKlaus SchrueferJörg BertholdPublished in: ESSCIRC (2007)
Keyphrases
- cmos technology
- low power
- power dissipation
- power consumption
- logic circuits
- high speed
- low cost
- mixed signal
- nm technology
- single chip
- vlsi circuits
- chip design
- low power consumption
- low voltage
- vlsi architecture
- digital signal processing
- power reduction
- high power
- gate array
- ultra low power
- parallel processing
- delay insensitive
- wireless transmission
- power saving
- cmos image sensor
- design process
- signal processor