Noise Margin in Low Power SRAM Cells.
Stefan CservenyJean-Marc MasgontyChristian PiguetPublished in: PATMOS (2004)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- high power
- low power consumption
- digital signal processing
- noise level
- vlsi circuits
- energy dissipation
- wireless transmission
- cmos technology
- logic circuits
- vlsi architecture
- power reduction
- signal to noise ratio
- nm technology
- gate array
- mixed signal
- power management
- power dissipation
- noise model
- message passing
- wireless communication
- real time