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Application of Hardware Architecture of Genetic Algorithm for Optimal Packet Scheduling.

Rong-Hou WuYang-Han LeeShiann-Tsong SheuHsien-Wei TsengMing-Hsueh ChuangYung-Kuang Wang
Published in: JCIS (2006)
Keyphrases
  • genetic algorithm
  • hardware architecture
  • neural network
  • pattern recognition
  • real time
  • artificial neural networks
  • efficient implementation